Negative bias temperature instability is an important reliability problem in electronic industry. The Static RAM based structures
within the microprocessor are mostly susceptible to NBTI because one of the pMOS transistors in the memory cell always has an
input of Zero. Here we propose a technique called Recovery Boosting that provides both pMOS transistors in the memory cell to be
bring into the recovery model. Evaluate the circuit-level design of coarse and fine grained recovery boosting techniques. Then
conduct an architecture-level verification of the performances and the reliability of using area-neutral designs of physical register files
and the issue queues. T his shows that Coarse Grained Recovery Boosting provides significant improvement in speed while having
very little impact on power consumptions and the performances.