FIR filters are being designed using HDL languages to enhance the speed of the system. In the whole system if the speed of the
individual block is enhanced, the overall speed of the system is enhanced. In order to obtain effective utilization hardware is done by
applying the pipelining technique. Pipelining is an implementation technique in which multiple instructions are overlapped in
execution. The proposed design of this paper is an attempt to optimize the system speed with minimal cost and hardware. In a filter the
pipelining of multiplication is achieved by shifts and addition method. Pipelined technique may reduce area, delay and enhance speed
as compared to common sub-expression elimination algorithm.