In this paper, a modified Dual Dynamic Flip-Flop by using edge triggering with a novel embedded logic module is introduced. It
presents speed efficient method to incorporate complex logic functions into the flip-flop with small delay penalty. The proposed
design reduces the power consumption up to 20% compared to the conventional flip-flops. The aim is to reduce the large delay,
leakage power and to reduce the power dissipation by reducing the precharge capacitance. Also, the design is compared with other
state-of-the-art designs. A high speed ring counter using digital CMOS gate logic components by the DDFF structure is also designed
which is well suited for modern high performance circuits. Finally simulation results are tested using TSPICE.