BUILT IN SELF TEST (BIST) can effectively reduce the difficulty and complexity of VLSI testing. A reconfigurable Johnson
counter and a scalable SIC counter are developed to generate a class of minimum transition sequences. The performances of the
designed TPGs and the circuits under test with 45 nm are evaluated. Simulation results with ISCAS benchmarks demonstrate that
MSIC can save test power and impose no more than 7.5% overhead for a scan design. In this paper an accumulator-based 3-
weight test pattern generation scheme is presented; the proposed scheme generates set of patterns with weights 0, 0.5, and 1.
Since accumulators are commonly found in current VLSI chips, this scheme can be efficiently utilized to drive down the
hardware of BIST pattern generation, as well. Comparisons with previously presented schemes indicate that the proposed scheme
compares favorably with respect to the required hardware.