DESIGN OF DOUBLE TAIL COMPARATOR FOR ANALOG TO DIGITAL CONVERSION

Comparator plays a major role on the overall performance of high speed analog to digital converters. A clocked comparator has to find
out whether the input signal is high or low at every clock cycle. Since it acts as interface between the analog and digital signal, the
accuracy is given by its input referred offset voltage, essential for the resolution of high performance ADC’s. Based on the analysis of
working of two different types of comparator it’s found that time taken for the capacitive charging and discharging is found high. So
in order to reduce the circuit delay we are going to use two tail transistor , as one at the top vdd and other at bottom vss, by including
this transistor positive feedback during regeneration is strengthened, which result in remarkable reduce in delay time. In the proposed
comparator, power consumption and delay are reduced significantly. The 0.18-?m CMOS technology post layout simulation confirms
the result.